You should see the follow Truth Table on the screen.Add the x.X value to the Truth Table the click OK. For digital circuits, both Truth Table and Timing Diagram are appropriate choices. The proper display to select is governed by the type of circuit simulated. With the Components tab selected in the left window, and diagrams selected from the top drop-down box, all of Qucs’ simulation output displays are visible.This window will be used to display our simulation results. If the simulation is successful, a new blank window will open. If errors occurred, you must correct them and re-simulate. Press F2 function key to start the simulation.Use a proper name like andGateSimulation.sch. Change the time parameter to 3 1 + 2 ( sum of all digital sources times). Double click on the digital simulation component and change the property Type to TimeList instead TruthTable. Add a digital simulation component into your circuit. Under the Components tab in the left window, select simulations from the drop-down box.Now double click on the digital source a and change its times parameter to 2ns 2ns.You should have some thing like image below. Uncheck display in schematic check box for the variable Num for each digital source. Rename each digital source to match the port name. Add two digital sources next to each sub circuit input. Select digital source located at the top of the resulting list. In the Components tab of the left window, select digital components from the top drop-down box.Now the new component should be loaded as below.Double click on the file component and browse to select your circuit saved on the step 9.
Select file component in the top drop-box and add a Subcircuit component to the schematic windows. Select the Components tab in the left window.Left click on New schematic tool or menu File > New.We can now assemble this digital circuit. Everything up to this point has been to create a sub-circuit, from our VHDL code, that can be simulated in a digital circuit.Finally Save it and give the file the same name as the entity (i.e.: andGate.sch). Right click in the component and select again the Edit Circuit Symbol option to back to the schematic. using the text tool create the port name text (a, b and x) drag it close to each correspondent pin as below. Right click in the component and select Edit Circuit Symbol.Rename the ports for match to the VHDL entity ports (a, b and x). Uncheck display in schematic check box for the variable Num for each port. For this specific schematic port a and b are inputs and x is an output. Double click on each port and change it type for in or out depending on the port function. Change the component name to match you VHDL device. Double click on the new VHDL file component and browse to select your vhdl code.On the digital components list select the VHDL file component. Select on left pane Components and on the dropdown menu select digital components. Now select or create an untitled schematic.After saved the editor will enable the syntax color highlighting which is very useful. use as file name the save name of the HDL entity. all entity andGate is port ( a, b : in std_logic x : out std_logic ) end andGate architecture hardware of andGate is begin x Save as. Project: AND Gate VHDL simualation - 2018 by Vanderson Pimenta - library ieee use ieee.